Does this video show you any angles of the PSU?

Yep, thanks! It shows the flange reinforcing/supporting the fan side of the PSU can. Does air enter the surround at the top and then is exhausted out that vent at the back of the surround? Hinkiness if so!

I see a nice chunk of the 150 W available power never makes it down the supply cable to the TAM CPU. That amplifier board for the sub looks overdone to the max. Does the TAM sub sound all that much better than that in the 6500? I sure hope so.

Power hogging components of 140 W TAM PSU:
Sub's Amplifier Board
Sub
Powered(?) stereo woofer pair and tweeter?
CPU unit's speaker amplifiers?
LCD
LCD controller board.

They should really have used the 6400's 220 W PSU. :rolleyes:

Thanks!

Interesting, but don't think it's the Beige G3 DT PSU, as it's listed at 230 W maximum continuous in the ServiceSource. I'll have to pull my 6500 PSU apart to compare the innards to those pics.

Makes no sense to me, but maybe Apple really did do a custom PSU for the TAM? If so, my PicoPSU supercharger notion might be the only reasonable line of development? Especially so if you cannot open that base unit without damage. That thing is a ridiculous, all but hermetically sealed kluge.

Trying to keep things as simple as possible, I sourced a six inch right angle FW M->F pigtail cable to match to the 12 inch RA USB M-F pigtail cable on hand.

Looking at my original TwinSlot Riser setup, I'd figured a setback increase was in order. Experimentation proved that an additional .3" of setback would be required in order to make use of readily available, off the shelf cables for adherence to KISS principle.

Here are pics of the 6360/TAM backplane template lashup, I'm very pleased:



Cables exit thru the vestigial PDS Slot access panel. Routing the cables out thru the TAM's CSII Card panel will be much easier.





Cable routing: top right oblique view. The second USB slot is occupied by a soldertail plug nubbin, no need for that approach now.




Cable routing: top left oblique backside view shows TAM template where cables will exit the CSII panel opening.

Guess pic limit reached, TBC.

Top View of same, 6360 is great, can still use the CSII NIC along with the additional PCI TwinSlot gambit. A USB WiFi Thimamajig attached to a powered hub, fed from the pigtail should be something like 10% better throughput than the CSII 10bT card, no?




TAM Tent Template shows the CSII backplane access panel, far easier to rout USB/FW400 pigtails thru there, though not difficult at all in my 6360 Testbed. Project is directly aimed at my 6360 and the AIO versions of Alchemy and Gazelle machines. Testbed status for TAM is just icing on the cake and a TAM fanatic clickbait teaser. [grimacing-face]





Overall view, note the angled "sides" of the Twinslot Riser. It now fits withing the 10cm x 10cm SEEED square! :D


To the TAM crowd: can someone measure the from the inside of the backplane to left inside of the FatBack setup, please? My TEMPOtrio measures 8 1/16" across, but it's probably the largest card anyone might wish to put in a TAM? My Tango2 is tiny by comparison.


DevNote says Gazelle machines (TAM) has ATA-2 (ATA-33?) interface, trio has ATA-133 (ATA4?) which was why I snagged a pair eons ago. Now that their bugginess in Gazelle has been subdued, the 6360 will have a Gazelle board upgrade.

Hoping an ATA-133 RAID array will make a huge improvement in performance. How might that compare to using a SATA card?

Has anyone got info on doing a 24pin ATX power cable conversion for the Alchemy/Gazelle machines? I'd imagine that reworking the cable lines would be the minimum required. Soft power would be nice, but not necessarily required?

Went a little wild on the 6360 side of things today. :D



In the day, I bent the harness backstop on the bottom of the Optical Bay up and removed the speaker so I could slide a full length Radius Thunder card thru above the harness. Elongated TriSlot Riser should do the same from the looks of it.

Backplane for the third card bracket shown for scale only. That's a 7" Card up front and looks to be room for a 5.5" card or so up in the Speaker Well.

TLDR Tales:
Length depends on how much room the Optical Harness takes up. ISTR I had to lay that back towards the front. Didn't matter because I had and external Burner by then. I moved the speaker into the vacated Optical Bay cubic. Have vague memories of snaking a VGA cable into the Tuner Bay opening to mate with the VGA Adapter on the forward relocated Video/Sound/Power Button board.

It was one hella mess inside, with all plastics removed for better ventilation thru the side panels. But 21" worth of 1600x1200 right off the bat and a bit later on an L2/G3 made a really nice low budget graphics workstation for the shop. Nor too shabby for a MUG connection 6360 refurb!

It got me online on and off at the MLA. It was so cranky that one of my customers gifted me with a DA/466 to put me out of its misery!

Well that may have been ridiculous, but it made a good start for exploring Daniel's notion of implementing a PCI Card on the 6400 riser. Maximized PCB Real Estate study with PGA Prototyping interconnect for development. SATA seems to be the consensus for such things.



Looks to be a bit of room on my 6360/5x00 TwinSlot Riser! Boards are life size for printout in .PDF

I had some PGA connectors in stock so I checked if they'd fit the 6360/5x00 and TAM risers I've been working on. Daniel over at the MLA suggested implementing a PCI device on the 6x00 Riser. Is there a better way than PGA to mount a PCI daughtercard on a riser in a DrawerMac?

CSII->PCI Oddities?

Curiouser and curiouser . . .



If interrupt lines are tied together on the logic board, how does this compute?



Do all, or only Bridge 3 have Direct Access to Memory Controller?

Screenshots from the 1996, first edition of DPCIaDfPMC linked in previous post. Which is devoid of later Gazelle and New World pollution. ;)

>> Trash80toG4 said:

Do all, or only Bridge 3 have Direct Access to Memory Controller? Click to expand...

All bridges have the same access.
I don't have a ROM with Open Firmware code that mentions a bridge 3. Maybe it exists in an Apple Network Server? Or some kind of prototype machine?
Bridge 0 is usually @F000000
Bridge 1 is usually @F200000
Bridge 2 is usually @F400000
Bridge 3 is usually @F600000

Thanks! Toying with the notion of getting CSII converted to PCI on one of the CABLE Risers for laughable playtime later or in the morning. It's on the way to checking out Slot_B conversion on the Riser and then on to Slot_C shenanigans.

Still curious how "INTA#, INTB#, INTC#, INTD# wires combined by OR per slot to provide a unique slot interrupt for each card." can work if the interrupts are tied together on the logic board? What's the significance of that INTA# nomenclature?

@Androda I figure you know which interrupt is used on CSII? Maybe that can help narrow things down for the Slot_C search?

>> Trash80toG4 said:

Still curious how " INTA#, INTB#, INTC#, INTD# wires combined by OR per slot to provide a unique slot interrupt for each card. " can work if the interrupts are tied together on the logic board? What's the significance of that INTA# nomenclature? Click to expand...

Every slot has 4 interrupt pins A,B,C,D. These may be reordered per slot. Usually a PCI card uses int A. Int A may be connected to int A or B or C or D on the motherboard or riser because of the reordering. A multifunction card may use more of the interrupt pins (A,B,C,D). None of that matters, since the Mac combines all interrupts from a slot to a single interrupt bit in one of the Mac's registers. When an interrupt for a slot happens, the OS interrupt handler sees the interrupt bit has changed and just needs to ask the driver for each device downstream of the corresponding slot if the interrupt belongs to it. The device driver checks an interrupt bit of one of the device's registers to determine if the interrupt belongs to it.

So why is Riser Slot_B, INTC wired to Reserved_A9?

I'm down to only a single reserved line unaccounted for on the motherboard connector.
Hoping that'll act in the same manner as Reserved A9 -> INTC does for Slot_B when connected to INTA, INTB or INTD?

There it is, "Reserved" Pin A11 of the PCI Spec is defined in the 6500 schematic as Interrupt for Slot_C, or so it would seem! A9 is defined as I buzzed out on the Riser for Slot_B as well.



A11 = PCI_SLOT3_INT (7,12,21)
A9 = PCI_SLOT2_INT (7,21)

Dunno what the numbers mean, but that's enough for tonight!

>> Trash80toG4 said:

So why is Riser Slot_B, INTC wired to Reserved_A9? Click to expand...

The schematic for J8 of the 6500 says the reserved pins are for a PCI adapter card. I suppose the PCI adapter card is an Apple specific adapter so it can do weird stuff like requiring reserved pins to handle separate interrupts.

Where's the schematic for the riser (PCI adapter card?)? Are you sure its INTC at A7 of slot_B? Is INTA at A6 of slot_B wired to something? I think every slot needs to have all INTA,B,C,D wired to something, otherwise a PCI device that uses one of those interrupt lines won't work.

J8 by itself ties INTA#, INTB#, INTC#, INTD# together for PCI_SLOT_INT. This is for a normal PCI card that is not the Apple PCI adapter card riser thingy or for one of the slots on the riser. For additional slots on the riser to work, reserved pins are used from J8.

>> Trash80toG4 said:

There it is, "Reserved" Pin A11 of the PCI Spec is defined in the 6500 schematic as Interrupt for Slot_C, or so it would seem! A9 is defined as I buzzed out on the Riser for Slot_B as well. View attachment 17710 A11 = PCI_SLOT3_INT (7,12,21) A9 = PCI_SLOT2_INT (7,21) Dunno what the numbers mean, but that's enough for tonight! Click to expand...

The numbers are page numbers in the schematics that tell you where the signals go.
7 is for OHare.
12 is or NVRAM, Cache slot, misc. term.
21 is for Pullups, Pulldowns.

page 7 OHare shows PCI_SLOT3_INT.
page 7 OHare says there's five REQ/GNT pairs. There doesn't seem to be a pair for PCI_SLOT3? Does that mean PCI_SLOT3 can't be a bus master? Are there any useful PCI cards that are not bus masters? A graphics card without 2D or 3D acceleration doesn't need to be a bus master. Graphics cards in Open Firmware don't need to be a bus master.