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| Testers Needed: Modified ROM for LC475/Q605 |
Forums > Vintage Apple > Add-ons, Peripherals & Networking
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frontein1 Tinkerer -------- Joined: Aug 27, 2025 Posts: 17 Likes: 27 |
Aug 27, 2025 - #1
For those with LC475/Q605-type Macs (ROM checksum FF 74 39 EE), a working SIMM slot, a SIMM programmer, and an available 8MB SIMM..... I would appreciate feedback on the attached ROM.
Firstly, thanks goes to @JDW @Jockelill and @WillJac for doing some initial testing and providing feedback. An important lesson we learned during testing is to fully reset your PRAM before using a new ROM. Especially if the new ROM uses PRAM settings (such as this one). Secondly, I want to specifically point out that I am using a modified version of the CDEV (control panel) that Garrett's Workshop developed. I trimmed down the control panel a little bit, and I plan to eventually make a new one from scratch. But they have a really nice CDEV that works for this initial testing. I have tried reaching out to them for permission to share, so if you have a contact for Zane or Garrett please share this posting with them. If they prefer, I can spin up a new CDEV and not use their version. This ROM has the following hacks that have been documented previously (I am using the driver name "ROMDISK"): **** You can use R (ROM) or RA (RAM) to boot accordingly # 1) offset 1278 = Open ROMDISK driver during boot # 2) offset 1706 = Treat ROMDISK as floppy # 3) offset 4742A = Disable ROM checksum # 4) offset 47908 = Disable memory test # 5) offset 47A20 = Disable memory test # 6) offset 79256 = Hard code ROM size for 24-bit/32-bit modes # 7) offset 80599 = Patch MMU table for 8MB ROM # 8) offset 805D9 = Patch MMU table for 8MB ROM # 9) offset 814E5 = Patch MMU table for 8MB ROM In addition, I have added the following: # 1) offset 60080 = ROMDISK Resource Header (not using NETBOOT or ATBOOT, this is a FREE resource in the stock ROM) # 2) offset 600B0 = ROMDISK Driver Header # 3) offset 61000 = PRAM Repair Bit (01) to set mouse speed to max and volume to 3 during boot # 4) offset 61010 = ROM/RAM disk size (currently 00 70 00 00; set to 00 30 00 00 for example if you intended to append a 3MB image and use a 4MB SIMM) # 5) offset 61020 = ROM/RAM disk start offset, probably does not need to be changed The CDEV will allow you to do the following (assuming you have a good PRAM battery): # 1) Mount/not-mount ROM or RAM disk if booting from another device # 2) Automatically boot from ROM or RAM disk Important info re: offset 61000 in the ROM ("PRAM Repair Bit"): This is new, and I have been discussing this on another thread here. If this Byte is set to 01, this will automatically set the mouse to the max speed AND the volume to 3. This offset is part of the ROM/RAM disk driver, and will be loaded before any INITs. If you do not want this functionality, make sure to set this Byte to 00 before burning your SIMM. Depending on if you use the ROM or RAM version of the disk, you should also notice a different icon in the Finder. I am calling this version 0.91 based on previous work. Please test away and provide feedback!
Liked by JockelillandJDW |
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JDW Administrator Japan -------- Joined: Sep 2, 2021 Posts: 2,534 Likes: 1,981 |
Aug 27, 2025 - #2
Folks,
This Universal ROM SIMM will kill the RAM checking at cold boot, which can save you a lot of time if you have something larger than a 32MB SIMM installed in an LC575 board (which in my case is a Color Classic MYSTIC. I simply soldered a ROM socket onto the motherboard pads. No drilling or complex hacks required. The ROM does more than just that, of course. Its features are similar to high end ROM SIMMs like you'll find from Garrett's Workshop. I think it's pretty fantastic. @frontein1 did a lot of work on the driver and firmware side, and his efforts deserve high praise! |
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frontein1 Tinkerer -------- Joined: Aug 27, 2025 Posts: 17 Likes: 27 |
Aug 29, 2025 - #3
Very kind words @JDW! Thank you.
I have a laundry list of future hacks I want to implement. I am looking at building in an optional routine to bypass counting the onboard memory, and to speed up the refresh rate of the RAM SIMM to use 60ns. I am particularly excited to get this hack working ;) Liked by JDW |
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JDW Administrator Japan -------- Joined: Sep 2, 2021 Posts: 2,534 Likes: 1,981 |
Aug 29, 2025 - #4
@frontein1
I just noticed that your opening post here and your post on the MLA makes no specific mention of the LC575, and while that is probably included in the "LC475/Q605-type Macs" phasing, it might be good to edit-in all the compatible Mac models for clarity. The reason I suggest that is because olePigeon said he can't test the ROM SIMM because he doesn't have an LC475 or Q605. Who knows... He might have an LC575 or other compatible Mac. By the way, I think it was @Willj or possibly @Jockelill who sent me the ROM SIMM Socket that I soldered into my LC575 motherboard, but I don't believe CayMac will be selling those sockets, so is there a recommended vendor of those, for people who want to buy one? |
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Willj Tinkerer -------- Joined: Apr 28, 2022 Posts: 69 Likes: 48 |
Aug 29, 2025 - #5
Liked by JDW |
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frontein1 Tinkerer -------- Joined: Aug 27, 2025 Posts: 17 Likes: 27 |
Aug 29, 2025 - #6
@JDW had a really good idea regarding this thread. This was to be more verbose in the machine models that could be used for each ROM.
So on the attached file, this is ROM checksum FF 74 39 EE. This ROM has a 7MB disk appended, so you will need an 8MB SIMM. Any of the machines listed below should be shoe-in candidates for testing:
Liked by JDW |
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frontein1 Tinkerer -------- Joined: Aug 27, 2025 Posts: 17 Likes: 27 |
Aug 29, 2025 - #7
Liked by JDW |
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frontein1 Tinkerer -------- Joined: Aug 27, 2025 Posts: 17 Likes: 27 |
Aug 30, 2025 - #8
Attached is ROM checksum F1 A6 F3 43. This ROM has a 7MB disk appended, so you will need an 8MB SIMM. Any of the machines listed below should be shoe-in candidates for testing:
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frontein1 Tinkerer -------- Joined: Aug 27, 2025 Posts: 17 Likes: 27 |
Aug 30, 2025 - #9
Just to point out, you can easily change the size of the disk image on these ROMs if you do not have an 8MB SIMM. Just change the following offset to the disk size you will be using, and append a different disk image. I will write up an instruction manual soon :)
offset 61010 = ROM/RAM disk size (currently 00 70 00 00; set to 00 30 00 00 for example if you intended to append a 3MB image and use a 4MB SIMM) Liked by JDW |
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Willj Tinkerer -------- Joined: Apr 28, 2022 Posts: 69 Likes: 48 |
Aug 30, 2025 - #10
Liked by frontein1andJDW |
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Willj Tinkerer -------- Joined: Apr 28, 2022 Posts: 69 Likes: 48 |
Aug 30, 2025 - #11
Here is the video link
Liked by frontein1 |
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frontein1 Tinkerer -------- Joined: Aug 27, 2025 Posts: 17 Likes: 27 |
Sep 1, 2025 - #12
Attached is ROM checksum 42 0D BF F3. Any of the machines listed below should be shoe-in candidates for testing:
Liked by JDW |
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frontein1 Tinkerer -------- Joined: Aug 27, 2025 Posts: 17 Likes: 27 |
Sep 7, 2025 - #13
Taking an idea from user @Mustermann on the 68kmla, I have a new version for the LC475/Q605 which bypasses counting the onboard memory. See link below.
https://68kmla.org/bb/index.php?threads/lc475-disable-onboard-ram.49016/ At offset A027C I basically just jump to offset 61030 in the ROM and perform the logic there to bypass 4MB banks. There is an inherent weakness I think in this approach, and that is if you ALSO have a 4MB SIMM installed. So this is something I want to fix. But importantly I think this will give us an opportunity to really dig into the MEMCjr IC to speed things up a bit with timing, etc. On my machine I have a 128MB RAM SIMM, and I only see these two banks each now being filled. Importantly, About now shows 128MB instead of the previous 132MB. So on the attached file, this is ROM checksum FF 74 39 EE. Any of the machines listed below should be shoe-in candidates for testing:
Liked by JockelillandJDW |
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JDW Administrator Japan -------- Joined: Sep 2, 2021 Posts: 2,534 Likes: 1,981 |
Sep 7, 2025 - #14
@frontein1
I have two questions: QUESTION #1 Mustermann's thread on the MLA says he wanted to DISABLE the soldered 4MB of motherboard RAM. Your previous message says the "About..." dialog on your machine now shows only 128MB instead of 132MB, which indicates your v092 file does indeed make the Mac ignore its soldered-on motherboard RAM (4MB). Does that mean your v091 and earlier ROM firmware bypasses ONLY the RAM SIMM checks at cold boot but doesn't also bypass the checking of the soldered 4MB of RAM? QUESTION #2 Did you create the v092 firmware primarily so we overclocking lovers can use a faster RAM SIMM to possibly overclock the CPU higher and be more stable than if the slower soldered RAM were enabled? (Some time ago, I discussed a possible benefit to that in the 475 Overclock thread here. I don't always get a stable machine at a 50MHz overclock and have long wondered if the slower 70ns soldered RAM was one reason why.) |
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frontein1 Tinkerer -------- Joined: Aug 27, 2025 Posts: 17 Likes: 27 |
Sep 7, 2025 - #15
Also I wanted to point out the following. You can confirm what version of the ROM/Driver you are using by pulling up the Get Info on the ROM/RAM disk.
Liked by JDWandNitram78 |
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frontein1 Tinkerer -------- Joined: Aug 27, 2025 Posts: 17 Likes: 27 |
Sep 9, 2025 - #16
Here is the "proof" that the v092 ROM for the Q605/LC475 (above) bypasses counting RAM bank 0 (slow onboard chips). Over the next couple days I am going to work on the Config register to see if I can get the MEMCjr to address the RAM at 60ns with the onboard chips disabled. (If you read the config bits below, the system is still addressing the RAM at 80ns by default).
1) This picture is a boot with the STOCK ROM. Notice that the system has counted 4MB (100) of RAM in Bank 0. 132MB total (4+64+64). 2) This picture is a boot with the v092 ROM. Notice that the system has bypassed Bank 0. 128MB total (0+64+64).
Liked by ericandJDW |
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frontein1 Tinkerer -------- Joined: Aug 27, 2025 Posts: 17 Likes: 27 |
Sep 10, 2025 - #17
OK I ran an initial benchmark with extensions disabled on my LC475/Q605 with v092 of the ROM. Remember this version has the onboard chips disabled. I borrowed that hack from @Mustermann, and I also borrowed his LC475SetCPUClock program. But I made one change to the Config register bits for 40MHz. I changed bit 3 from 1 to 0 to allow 60ns RAM access. I believe this is safe since I am not using the onboard chips.
I am going to start ratcheting up the CPU frequency now to see how high I can push it with it still being stable. 1) v092 with no MEMCjr changes on LEFT; v092 with MEMCjr 40MHz & 60ns RAM on RIGHT 2) Bit level comparison of BEFORE and AFTER
Liked by ericandJDW |
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JDW Administrator Japan -------- Joined: Sep 2, 2021 Posts: 2,534 Likes: 1,981 |
Sep 10, 2025 - #18
Holy cow! All the numbers are improved across the board!
I'm going to tag @YMK because he is the creator of Synchr030/S which is an accelerated PDS RAM card for the SE/30. I'm also going to tag @Willj and @Jockelill who I know are following your incredible work. Liked by Jockelill |
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Fizzbinn Active Tinkerer Charlottesville, VA -------- Joined: Nov 29, 2021 Posts: 256 Likes: 262 |
Sep 10, 2025 - #19
Very Interesting! Am I interpreting correctly, the improvement shown in the graphs is both going from 25MHz to 40MHz and enabling 60ns RAM access? If so, it would be awesome to see the difference without the overclock and just with the overclock.
Liked by JDW |
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frontein1 Tinkerer -------- Joined: Aug 27, 2025 Posts: 17 Likes: 27 |
Sep 10, 2025 - #20
@zigzagjoe pointed out to me on the 68kmla that Norton Utilities would be a better benchmark. So as I work on bumping up the frequency I will use that program to run out some more benchmarks. Liked by FizzbinnandJDW |
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